Voltage switching in a memory device

ABSTRACT

Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

RELATED APPLICATION

This is a continuation of U.S. application Ser. No. 12/775,131, titled “VOLTAGE SWITCHING IN A MEMORY DEVICE” filed May 6, 2010 now U.S. Pat. No. 8,217,705 (allowed) which is commonly assigned and incorporated herein by reference.

TECHNICAL FIELD

The present embodiments relate generally to memory and a particular embodiment relates to voltage switching in a memory device.

BACKGROUND

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

A flash memory is a type of non-volatile memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array that includes a large number of memory cells. Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are typically grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. The charge can be removed from the charge storage structure by an erase operation.

Certain memory operations in a non-volatile memory device use high voltages (e.g., greater than a device supply voltage) on the control gates of the memory cells. For example, programming memory cells might use voltages in the range of 15V-20V. These voltages need to be switched from the high voltage sources (e.g., charge pumps) to the various circuits of the memory device that need the high voltages.

Two circuit architectures are typically used to perform the high voltage switching in non-volatile memory devices: local pump high voltage switches (LPHVSW) and self-boosting high voltage switches (SBHVSW). Both of these architectures have their respective drawbacks.

An LPHVSW architecture, illustrated in FIG. 1, uses a local boosting charge pump 100 to generate the control voltage of a high voltage MOS pass transistor 101. In this architecture, SW_(out)=SW_(in)−V_(thSHV) when V_(g) is boosted to SW_(in), where SW_(out) and SW_(in) are the output and input voltages respectively, and V_(thSHV) is the threshold voltage of the MOS transistor 101. In order to obtain SW_(out)=SW_(in), a V_(g) that is greater than SW_(in) is used.

This circuit generally drives large, critical parasitic elements that are sensitive to layout configurations, high voltages applied to some circuit nodes, and a clock generator with a switching speed that is dependent on a clock frequency. These drawbacks of the LPHVSW architecture can limit the performance of high voltage multiplexers, such as the global word line driver of a memory array.

An SBHVSW architecture, illustrated in FIG. 2, uses a combination of a high voltage depletion-mode NMOS transistor 200, with a threshold voltage that is less than 0V, and a high voltage PMOS transistor 201. In the illustrated circuit, when enb=0V, then SW_(out)=SW_(in). Thus, this circuit provides reduced operational voltages compared to the circuit of FIG. 1. However, the circuit of FIG. 2 lacks bi-directionality and experiences a reverse leakage of current when used in an SBHVSW voltage multiplexer.

For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a voltage switch with improved performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of a typical prior art local pump high voltage switch circuit.

FIG. 2 shows a schematic diagram of a typical prior art self-boosting high voltage switch circuit.

FIG. 3 shows a schematic diagram of one embodiment of a high voltage switch circuit.

FIG. 4 shows a block diagram of one embodiment of a portion of a memory device configured to incorporate the high voltage switch circuit of the embodiment of FIG. 3.

FIG. 5 shows a block diagram of one embodiment of a memory system configured to incorporate the high voltage switch circuit of the embodiment of FIG. 3.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.

FIG. 3 illustrates a schematic diagram of one embodiment of a high voltage switch circuit based on level shift circuits. The illustrated embodiment is comprised of two switch circuits 320, 321 coupled in series. These circuits provide the switching of the SW_(IN) voltage to the SW_(OUT) output. A first level shift circuit 310 is coupled to an input of a first switch circuit 320. A second level shift circuit 311 is coupled to an output of a second switch circuit 321. An enable signal circuit 390 is coupled to the level shift circuits 310, 311 to provide the different states (e.g., a logical high component and a logical low component) of the enable signal to the various circuit components.

The level shift circuits 310, 311 drive the gates of the transistors of their respective switch circuits 320, 321. For example, the first level shift circuit 310 (e.g., input level shift circuit) generates the NSW_(IN) and the PSW_(IN) signals. The NSW_(IN) signal drives the n-channel transistor N_(IN) 330 and the PSW_(IN) signal drives the control gates of the p-channel transistors 360 of the first switch circuit 320 (e.g., input switch circuit). The second level shift circuit 311 (e.g., output level shift circuit) generates the NSW_(OUT) and the PSW_(OUT) signals. The NSW_(OUT) signal drives the n-channel transistor N_(OUT) 331 and the PSW_(OUT) signal drives the control gates of the p-channel transistors 361 of the second switch circuit 321 (e.g., output switch circuit).

The level shift circuits 310, 311 have the relatively low voltage (e.g., 3V) signal inputs of ENOUT and ENOUTb and output the relatively high voltage (e.g., 20V) of SW_(IN) and SW_(OUT). Each level shift circuit 310, 311 includes two groups of series connected p-channel transistors 305-308. The input level shift circuit 310 includes SHP1 305 and SHP2 306 while the output level shift circuit 311 includes SHP3 307 and SHP4 308.

Each switch circuit 320, 321 and each level shift circuit 310, 311 are shown with four series coupled p-channel transistors in each circuit. This is only one possible embodiment for these circuits. Since each circuit has to drop a relatively large voltage (e.g., 20V) across the circuit, the greater the quantity of transistors in each circuit, the lower the maximum drain-to-source voltage (V_(DS)) experienced by each transistor.

The illustrated embodiment assumes a 20V input voltage that is to be switched. Thus, with four transistors in each circuit 310, 311, 320, 321, each transistor is expected to experience a maximum V_(DS) of 5V. Fewer transistors can be used in each circuit 310, 311, 320, 321 assuming the transistor can withstand a larger V_(DS). In the alternative, a greater number of transistors may be used in each circuit 310, 311, 320, 321 in order to use transistors having a lower maximum V_(DS). Typically, these types of p-channel transistors can be less expensive to manufacture since they require no additional processing for high voltage source/drain diffusions.

The substantially identical switch circuits 320, 321 and the substantially identical level shift circuits 310, 311 provide the bi-directionality to the high voltage switch circuit. Because of the inherent diodes of each circuit 310, 311, 320, 321 between series connections of transistor pairs, the second switch circuit 321 and the second level shift circuit 311 provide current flow in the opposite direction from the first switch circuit 320 and the first level shift circuit 310. At least one set of diodes of the circuits 310, 311, 320, 321 will thus be forward biased in one of two possible polarity situations (e.g., SW_(IN)>SW_(OUT) or SW_(IN)<SW_(OUT)). Additionally, when the switch circuit is turned off, a blocking series of diodes are reverse biased to provide leakage protection regardless of the voltage polarity between SW_(IN) and SW_(OUT).

The control signal SW_(EN) that turns the switch on and off can be provided by control logic. In one embodiment, SW_(EN) is at a logic high at 3V and a logic low at 0V.

Two modes of operation of the high voltage switch circuit are described subsequently. In the first mode, the switch is turned on and the voltage at SW_(IN) is passed on to SW_(OUT). SW_(OUT) may start at 0V and eventually rise to approximately SW_(IN) (within inherent losses of the activated transistors) if the load is capacitive. In the second mode, the switch is turned off and the voltage at SW_(IN) is not passed on to SW_(OUT). In this mode, SW_(OUT) remains substantially at 0V. An SW_(IN) of 20V is used subsequently in describing the operation of the high voltage switch circuit. This voltage is for purposes of illustration only as any voltage can be used.

The subsequent discussion assumes that SW_(IN)>SW_(OUT). However, the bi-directional nature of the switch allows the opposite to also be true.

Referring to FIG. 3, the switch is turned on by the control logic setting SW_(EN) to a logic high. This signal is applied to the first inverter 301 that generates the ENOUTb control signal at a logic low and the second inverter 302 that generates ENOUT at a logic high.

The logic low ENOUTb signal is applied to control transistors N1 350 and N4 353. The logic low ENOUTb turns these transistors 350, 353 off. Thus, the SHPT series of transistors 305 and the SHP4 series of transistors 308 are turned on so that NSW_(OUT)=SW_(OUT) and NSW_(IN)=SW_(IN)=20V, which turns on n-channel transistors N_(IN) 330 and N_(OUT) 331.

The logic high ENOUT signal is applied to control transistors N2 351 and N3 352. The logic high ENOUT turns these transistors 351, 352 on. Thus, the SHP2 series of transistors 306 and the SHP3 series of transistors 307 are turned off so that PSW_(IN)=0V and PSW_(OUT)=0V. PSW_(IN) and PSW_(OUT) being at 0V turns on the switch circuits 320, 321 respectively. Current I_(SWITCH) flows from SW_(IN) to SW_(OUT) and the diodes associated with the transistors of the first switch circuit 320 are reverse biased. The diodes associated with the transistors of the second switch circuit 321 are forward biased but do not conduct provided that I_(SWITCH)×RdsON<V_(be) where RdsON is the on resistance of each of the series coupled transistors of the second switch circuit 321.

The switch is turned off by the control logic setting SW_(EN) to a logic low. In this mode, the input voltage is not switched to the output so that, in the illustrated embodiment, SW_(IN)=20V and SW_(OUT)=0V.

A logic low SW_(EN) signal results in a logic high ENOUTb signal from the first inverter 301 and a logic low ENOUT signal from the second inverter 302. The logic high ENOUTb signal turns on control transistors N1 350 and N4 353. Thus, the SHP1 305 and SHP4 308 series transistors are turned off so that PSW_(IN)=SW_(IN)=20V and PSW_(OUT)=SW_(OUT). Since control transistors N1 350 and N4 353 are turned on, both NSW_(IN) and NSW_(OUT) are at 0V so that transistors N_(IN) 330 and N_(OUT) 331 are turned off, the switch circuits 320, 321 are turned off, and current I_(SWITCH) is not flowing.

The diodes associated with the transistors of the first switch circuit 320 are reverse biased. The diodes associated with the transistors of the second switch circuit 321 are forward biased. In this condition, the voltage difference SW_(IN)−SW_(OUT)=20V−0V=20V is almost entirely dropped across only the transistors of the first switch circuit 320. These transistors of the first switch circuit 320 should therefore have a maximum V_(DS) capability greater than SW_(IN)/(transistor quantity) in order to stop a breakdown that would cause a current flow through the switch.

The quantity of transistors that can be used in each of the switch circuits 320, 321 and level shift circuits 310, 311 can be determined by maximum voltage drop (V_(max)) across all of the transistors of each circuit 310, 311, 320, 321 divided by the maximum voltage that each transistor in each circuit can withstand (V_(dsmax)). In other words, V_(max)/V_(dsmax). Therefore, the greater the quantity of transistors in each circuit, the lower the voltage drop across each transistor of each circuit. In the illustrated embodiment, the maximum voltage that the switch is to handle is SW_(IN)=20V. If it is assumed that each transistor can withstand 5V prior to breakdown, the quantity of series coupled transistors in each circuit 310, 311, 320, 321 may be four or more. The embodiment of FIG. 3 shows each circuit 310, 311, 320, 321 having the same number of transistors. However, alternate embodiments that use different SW_(IN) voltages and/or different transistors having a different V_(ds) may use different quantities in each switch and level shift circuit.

FIG. 4 illustrates a block diagram of one embodiment of a portion of a memory device incorporating the high voltage switch circuit of the embodiment of FIG. 3. In one embodiment, the memory device includes a non-volatile memory array 400 such as flash memory.

In one embodiment, the memory array 400 is comprised of a NAND architecture array of floating gate memory cells. Alternate embodiments can use other types of memory architecture including NOR and AND. The memory array 400 is comprised of a plurality of access lines (e.g., local word lines) LWL<n:0> and data lines (e.g., bit lines) BL<m:0>. Each end of the series string of memory cells of the array 400 includes a select gate transistor. One end of the series string has a select gate drain transistor that is controlled by the select gate drain (SGD) line. The other end of the series string has a select gate source transistor that is controlled by the select gate source (SGS) line.

The SGD, SGS, and LWL<n:0> lines are driven by a string driver block 401 that drives the voltages for these signals. A memory block high voltage selector 420 controls the switching of high voltages to the string driver 401. The memory block high voltage selector 420 can incorporate a plurality of the high voltage switch circuits of the present disclosure.

An array driver 403 can also be comprised of a plurality of the high voltage switch circuits of the present disclosure. This array driver 403 is responsible for switching high voltages to the select gate drain, select gate source, and word lines of the memory array. The array driver 403 incorporates a global select gate drain driver 430, a global word line driver 431, and a global select gate source driver 432. The global select gate drain driver 430 drives all of the select gate drain lines of the memory array 400. The global select gate source driver 432 drives all of the select gate source lines of the memory array 400. The global word line driver 431 drives all of the global word lines of the memory array 400.

A global source line (GSRC) driver 411 controls the voltages applied to the source line of the memory array 400. A tub driver 410 controls the voltages applied to the semiconductor tub in which the memory array 400 is located.

High voltage regulators 423 regulate the unregulated high voltage from the charge pump generators 424. The regulated voltages from the regulators 423 are input over a high voltage bus 406 to the array driver 403 to be switched by the plurality of high voltage switch circuits of the present disclosure. The unregulated charge pump generator 424 voltages are also transferred, over a high voltage bus 405, to the high voltage switch circuits of the memory block high voltage selector 420 and to the global source line driver 411 and tub driver 410.

FIG. 5 illustrates a functional block diagram of a memory device 500 that can incorporate the embodiment of FIG. 4. The memory device 500 is coupled to an external processor 510. The processor 510 may be a microprocessor or some other type of controller. The memory device 500 and the processor 510 form part of a memory system 520.

The memory device 500 includes an array 530 of non-volatile memory cells. The memory array 530 is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array 530 are comprised of series strings of memory cells. As is well known in the art, the connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, a NOR architecture, or some other type of architecture.

Address buffer circuitry 540 is provided to latch address signals provided through I/O circuitry 560. Address signals are received and decoded by a row decoder 544 and a column decoder 546 to access the memory array 530. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 530. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device 500 reads data in the memory array 530 by sensing voltage or current changes in the memory array columns using sense amplifier circuitry 550. The sense amplifier circuitry 550, in one embodiment, is coupled to read and latch a row of data from the memory array 530. Data input and output buffer circuitry 560 is included for bidirectional data communication as well as the address communication over a plurality of data connections 562 with the controller 510. Write circuitry 555 is provided to write data to the memory array.

Memory control circuitry 570 decodes signals provided on control connections 572 from the processor 510. These signals are used to control the operations on the memory array 530, including data read, data write (program), and erase operations. The memory control circuitry 570 may be a state machine, a sequencer, or some other type of controller to generate the memory control signals. In one embodiment, the memory control circuitry 570 is configured to execute methods for switching high voltages in the memory device by controlling the high voltage switch circuit discussed previously.

The flash memory device illustrated in FIG. 5 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

Conclusion

In summary, one or more embodiments of the high voltage switch circuit switch voltages greater than a supply voltage from charge pumps to the memory array of a memory device. Two switch circuits, each comprised of groups of series coupled transistors, are coupled in series to provide bidirectional operation while the inherent diodes from the series connections provide blockage of leakage current when the switch is off. An input level shift circuit coupled to the input switch circuit and an output level shift circuit coupled to the output switch circuit drive their respective switch circuits by shifting a relatively low voltage control signal to a relatively high voltage output signal.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof. 

What is claimed is:
 1. A memory device comprising: an array of memory cells; and a voltage switching circuit coupled to the array of memory cells and configured to switch operating voltages to the array of memory cells, the voltage switch circuit comprising: a plurality of transistors configured to switch an input voltage at a switch input to a switch output as an output voltage, wherein a maximum voltage capability of each transistor and an expected maximum input voltage determines a quantity of the plurality of transistors; a first level shift circuit coupled to the switch input and configured to drive a first group of the plurality of transistors; and a second level shift circuit coupled to the switch output and configured to drive a second group of the plurality of transistors.
 2. The memory device of claim 1 wherein the first and second groups of the plurality of transistors each comprise a plurality of series coupled transistors wherein each transistor is coupled to an associated diode.
 3. The memory device of claim 1 wherein the quantity of the plurality of transistors is determined by the expected maximum input voltage divided by the maximum voltage capability of each transistor.
 4. The memory device of claim 3 wherein the maximum input voltage comprises a maximum voltage drop across all of the transistors of each group of the plurality of transistors.
 5. The memory device of claim 1 wherein the array of memory cells comprise one of a NAND architecture, a NOR architecture, or an AND architecture.
 6. The memory device of claim 1 wherein the first group and the second group of transistors comprise the same quantity of the plurality of transistors.
 7. The memory device of claim 1 wherein the first group and the second group of transistors comprise different quantities of the plurality of transistors.
 8. A memory device comprising: an array of memory cells; and an array driver coupled to the array of memory cells and configured to switch voltages to the array of memory cells, the array driver comprising a plurality of voltage switching circuits, each voltage switching circuit comprising: a plurality of transistors configured to switch an input voltage at a switch input to a switch output as an output voltage, wherein a maximum voltage capability of each transistor and an expected maximum input voltage determines a quantity of the plurality of transistors; a first level shift circuit coupled to the switch input and configured to drive a first group of the plurality of transistors; and a second level shift circuit coupled to the switch output and configured to drive a second group of the plurality of transistors.
 9. The memory device of claim 8 wherein the plurality of voltage switching circuits comprise a word line driver, a select gate drain driver, and a select gate source driver.
 10. The memory device of claim 9 and further comprising a string driver that couples the plurality of voltage switching circuits to the array of memory cells.
 11. The memory device of claim 10 wherein the word line driver, the select gate drain driver, and the select gate source driver are each coupled to an associated transistor of the string driver, wherein each associated transistor is enabled by a control signal.
 12. The memory device of claim 11 and further comprising a memory block high voltage selector coupled to the string driver and configured to generate the control signal.
 13. The memory device of claim 12 wherein the memory block high voltage selector comprises a plurality of the voltage switching circuits.
 14. A memory device comprising: an array of memory cells; memory control circuitry coupled to and configured to control the array of memory cells; and a plurality of voltage switches configured to switch voltages to access lines and data lines of the array of memory cells, each voltage switch comprising: a first switch circuit comprising a control transistor in parallel with a plurality of series coupled transistors and having a switch input; a second switch circuit comprising a control transistor in parallel with a plurality of series coupled transistors, the second switch circuit coupled in series to the first switch circuit and having a switch output; a first level shift circuit, coupled to the switch input, configured to drive the control transistor and the plurality of series coupled transistors of the first switch circuit; and a second level shift circuit, coupled to the switch output, configured to drive the control transistor and the plurality of series coupled transistors of the second switch circuit; wherein an input voltage coupled to the switch input is switched to the switch output.
 15. The memory device of claim 14 and further comprising a global source line driver coupled to a source line of the array of memory cells and configured to control voltage applied to the source line.
 16. The memory system of claim 14 and further comprising a tub driver coupled to a semiconductor tub comprising the array of memory cells, wherein the tub driver is configured to control voltages applied to the semiconductor tub.
 17. The memory device of claim 14 wherein each of the plurality of voltage switches comprise a first mode of operation and a second mode of operation wherein the first mode of operation is configured to pass the input voltage to the switch output and the second mode of operation is configured to provide substantially 0V at the switch output.
 18. The memory device of claim 14 and further comprising an inherent diode between each series connection of transistor pairs.
 19. The memory device of claim 14 wherein each voltage switch is configured to switch a voltage from the switch output to the switch input.
 20. The memory device of claim 14 wherein the first and second level shift circuits each comprise a pair of series connected transistors. 